EPIC ( )
( «EPIC ()»)
EPIC (. explicitly parallel instruction computing) . 1997 HP Intel[1] Intel Itanium.[2] EPIC , , . , .
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[] VLIW
1989 HP , RISC , . , EPIC.[2] VLIW, , .
EPIC , . , , , . (instruction level parallelism) .
VLIW , :
- VLIW . (, ), , ( ).
- (, DRAM) . - .
[] VLIW
EPIC VLIW:
- (bundle). , , . . , .
- (software prefetch). , , . , .
- , , (bypassing control dependencies), (bypassing data dependencies).
- (check load instruction) , . , .
EPIC (grab-bag) ILP ( ):
- , . , , . , , .
- , Not a thing . .
- , .
Itanium [3], (software pipelining). .[4]
[]
EPIC, Itanium.
- IMPACT Urbana-Champaign Wen-mei Hwu .
- PlayDoh HP-labs.
- Gelato, Linux Itanium.
[] .
- Complex instruction set computer (CISC)
- Reduced instruction set computer (RISC)
- Very long instruction word (VLIW)
- IA-64
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- Schlansker and Rau EPIC: An Architecture for Instruction-Level Parallel Processors (PDF). HP Laboratories Palo Alto, HPL-1999-111 (February 2000). 27 2012. 8 2008.
- 1 2 Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture. HP Labs (June 2001). 27 2012. 14 2007.
- C . 2. Intel Itanium, HP PA8700, Alpha
- De Gelas, Johan ItaniumIs there light at the end of the tunnel?. AnandTech (November 9, 2005). 27 2012. 8 2008.
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- Historical background for EPIC
- Mark Smotherman (2002) «Understanding EPIC Architectures and Implementations»
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CISC · EDGE · EPIC · MISC · URISC · RISC · VLIW · ZISC · · · |
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| DSP · GPU · SoC · PPU · · · | |||||||||
| Barrel shifter · FPU · BSB · MMU · TLB · · control unit · · · · ( ) | |||||||||
| APM · ACPI · Clock gating · | |||||||||
